About:
I am a sixth year graduate student in the electrical engineering department (computer engineering division) at Princeton University, completing my degree in April 2008. I will be joining the BlueGene team at IBM TJ Watson Research.
I have been working with professor Li-Shiuan Peh whose research focuses on interconnection networks (or networks-on-chip, NoCs), especially in the context of chip-multiprocessors (CMPs). My work has focused on high-level power modeling of interconnection networks and of CMPs, and on distributing cache coherence functionality within the network.
I have also taken a number of computer science classes both at Brown University and at Princeton, including software engineering, computer graphics, and computer vision, and I am particularly interested in opportunities which incorporate these disciplines.
Publications:
1. Noel Eisley, Li-Shiuan Peh, and L. Shang, “In-Network Cache Coherence,” in Proc. of the 39th Int’l. Symp. on Microarch. (MICRO-39), Orlando, December, 2006. pdf
2. Vassos Soteriou, N. Eisley, and L-S. Peh, “Software-Directed Power-Aware Interconnection Networks,” in ACM Trans. on Arch. and Code Optimization (TACO), to appear.
3. N. Eisley, V. Soteriou, and L-S. Peh, “High-Level Power Analysis for Multi-Core Chips,” in CASES-9, Seoul, South Korea, October, 2006. pdf
4. V. Soteriou, N. Eisley, Hangsheng Wang, Bin Li, and L-S. Peh, “Polaris: A System-Level Roadmap for On-Chip Interconnection Networks,” in Proc. of the 24th Int’l. Conf. on Comp. Design (ICCD), San Jose, October, 2006. pdf
5. N. Eisley, Li Shang, and L-S. Peh, “In-Network Cache Coherence,” In Computer Architecture Letters, March 2006. pdf
6. V. Soteriou, N. Eisley, and L-S. Peh, “Software-Directed Power-Aware Interconnection Networks,” in CASES-8, San Francisco, CA, September, 2005. pdf
7. N. Eisley and L-S. Peh, “High-Level Power Analysis of On-Chip Networks,” In Proc. of the 7th Int’l. Conf. on Compilers, Arch. and Synthesis for Embedded Systems (CASES-7), Washington D.C., September 2004. pdf
Tools:
LUNA: A high-level power analysis framework for on-chip networks which uses link utilization as an abstraction for power consumption.
Polaris (with Vassos Soteriou): A design exploration tool for future NoCs. It generates area, power, and latency estimates for an NoC with given topology and pipeline design. Related tool (by Vassos Soteriou): Trident.
Other Interests:
Sports: I enjoy participating in almost any sport, but particularly baseball, ultimate frisbee, and downhill skiing. You can see my ski racing results from 1999, 2000, 2001, and 2002. My teams are the Red Sox and the Patriots. If you are a Yankees fan, I hope that you will not hold this against me.
Photography: I like to take pictures of flora, fauna, and landscapes. I have a flickr page, which I share with my wife. I shoot Pentax *istDS and K10D digital SLRs. I like to collect used lenses on ebay.